Advanced Packaging Bottleneck: CoWoS Capacity Stalls AI Chip Output

Mizuho Securities Asia raised its forecast for TSMC's advanced CoWoS packaging capacity in late June, revising upward from a prior estimate of 80,000 wafers per month by end-of-2027 to a figure north of 90,000. The revision was driven by a single variable: AI server processor demand that is accelerating faster than any node shrink or fab build-out can match. The bottleneck in AI silicon is no longer transistor density, and it has not been for at least eighteen months. It is packaging.

The shift has been building since Nvidia's H100 ramp made CoWoS the de facto standard for attaching high-bandwidth memory to a compute die, but the scale of the mismatch only became undeniable in the first half of 2026. Every Blackwell-class GPU, every custom ASIC from the hyperscalers, and a growing share of AI-server CPUs now require some variant of advanced packaging that TSMC controls at the tooling, process, and capacity level. As DATAQUEST noted in its July survey of packaging trends, AI and HPC processor performance now depends not only on transistor density but also on memory bandwidth, I/O density, power delivery, and thermal management. Those four variables are all packaging problems.

CoWoS, which stands for Chip on Wafer on Substrate, is not a single process. The 'CoW' step places compute and memory dies side by side on a silicon interposer; the 'oS' step mounts that interposer onto a package substrate. The interposer carries the dense wiring that lets a GPU talk to six or eight HBM stacks with the bandwidth required to keep a trillion-parameter model's attention mechanism fed. TSMC's near-total dominance of CoWoS volume means that every major AI chip, from Nvidia's B200 and B100 to AMD's MI350X and Amazon's Trainium3, competes for the same limited interposer capacity at the same handful of fabs in Taiwan. That concentration is what turned a manufacturing step into a strategic chokepoint.

TSMC is not standing still. DigiTimes reported on June 30 that the company is accelerating CoWoS expansion while pushing a next-generation panel-level packaging technology called CoPoS, short for Chip on Panel on Substrate. The architecture moves from a round 300mm wafer format to a square panel, roughly 510mm by 515mm, increasing the usable area per panel by a factor of roughly 3.5x compared with a wafer. More usable area means more interposers per production unit, which lowers cost per chip and increases effective throughput. The supply chain for CoPoS equipment is under what DigiTimes described as a 'gag order,' with TSMC restricting what tool vendors can disclose publicly. That level of operational security is normally reserved for front-end process nodes, not packaging.

The panel-level transition matters because CoWoS on 300mm wafers has a geometry problem. A single reticle-limited interposer, the largest that can be patterned in one lithographic exposure, is roughly 26mm by 33mm. Larger interposers require stitching multiple reticle fields, which adds cost, complexity, and defect risk. CoPoS panels eliminate the round-wafer edge-loss and allow more interposers per sheet, but they require an entirely new ecosystem of lithography, deposition, and bonding tools sized for rectangular substrates. TSMC's equipment vendors, including those supplying temporary bonding and debonding, wafer-level underfill, and die-bonding tools, are being asked to qualify panel-compatible versions of their platforms on an accelerated schedule.

For any chip designer not named Nvidia, the CoWoS bottleneck presents a strategic question: wait in the queue behind the largest volume buyer of advanced packaging on the planet, or find an alternative. That question is what 24/7 Wall St identified in May as a structural opening for Intel's EMIB technology. EMIB, or Embedded Multi-die Interconnect Bridge, replaces the full silicon interposer with small silicon bridge chips embedded directly in the package substrate, placed only where the dense die-to-die connections are actually needed. A full interposer covers the entire footprint of all the dies; a bridge covers only the edges where two dies meet.

The architectural difference has cost and yield consequences. A large silicon interposer is expensive to manufacture and becomes a single point of failure for the entire multi-die assembly. If one of the thousands of through-silicon vias in the interposer is defective, the whole package is scrapped. EMIB's bridge approach limits the silicon to the connection zones and uses standard organic substrate for the rest, reducing the bill of materials and localising the yield risk. Intel has been shipping EMIB in volume since the Stratix 10 FPGA in 2019 and has since refined the technology across multiple product generations, including the Ponte Vecchio GPU and the Gaudi AI accelerators.

Intel's packaging push goes beyond EMIB. At the IEEE Electronic Components and Technology Conference in June, which drew more than 2,700 attendees to discuss advances in heterogeneous integration, Intel Foundry showcased EMIB-T, a variant that adds through-silicon via connections for vertical die stacking on top of the bridge, and co-packaged optics prototypes that integrate photonic chiplets directly into the package substrate alongside compute and memory dies. The company is also investing in glass-core substrates, which replace traditional organic build-up films with a glass panel that offers better dimensional stability, lower signal loss at high frequencies, and the ability to support finer line pitches.

Intel carved out its advanced packaging operations into a standalone division in June, a move MSN reported as positioning the unit to serve external foundry customers on equal footing with internal product groups. The reorganisation matters because it signals that Intel views packaging as a revenue line in its own right, not a support function. A fabless startup designing an AI ASIC that cannot get CoWoS allocation from TSMC until 2028 can now theoretically book EMIB capacity from Intel Foundry, assuming its design is compatible with Intel's bump pitch, bridge dimensions, and thermal envelope.

The memory side of the packaging story is moving just as fast. Hybrid bonding, which fuses copper pads on two dies at room temperature without solder microbumps, is transitioning from CMOS image sensors and 3D NAND to high-bandwidth memory. The density improvement over traditional microbump-based stacking is roughly an order of magnitude: hybrid bonding supports pad pitches below 1 micron, compared with roughly 30 to 40 microns for the microbumps used in today's HBM3E stacks. That density translates directly into more interconnect channels between logic and memory dies, which means higher bandwidth at the same power envelope, or the same bandwidth at lower power.

Samsung put hard numbers behind the thermal argument in June. At the company's foundry forum, Samsung engineers presented data showing that hybrid-bonded HBM stacks achieve roughly 20 percent lower junction temperature than equivalent microbump-based stacks at the same power density, TechTimes reported. The physics is straightforward: without the polymer underfill layer required by microbump bonding, the thermal path from the DRAM die through the copper hybrid bond to the logic die below it is shorter and has lower thermal resistance. For HBM4 and HBM4E, which will stack twelve or sixteen DRAM dies, heat removal is the limiting factor, not signalling speed.

SK Hynix, which holds an estimated 60 to 70 percent of HBM4 volume for Nvidia's Vera Rubin platform, is taking a different route for the near term. The company signed a multi-year co-development agreement with Nvidia covering HBM4 and beyond, The Next Web reported in June. SK Hynix is deploying what it calls iHBM, an intermediate cooling technology that reduces thermal resistance by roughly 30 percent without switching to hybrid bonding, buying time for the hybrid bonding tooling ecosystem to mature. BE Semiconductor Industries, the Dutch toolmaker that dominates the hybrid bonding equipment market, raised its long-term revenue target on June 18, citing accelerating demand from both memory and logic customers, Insider Monkey reported.

The Chiplet Interface Question

Beneath the interposer and bonding technology choices sits a quieter but equally consequential decision: which die-to-die interconnect standard a chiplet-based design commits to. The two leading contenders are UCIe, the Universal Chiplet Interconnect Express standard backed by Intel, AMD, Arm, and TSMC, and BoW, the Bunch of Wires standard from the Open Compute Project. Both carry parallel data across short physical distances at extremely high density, but they differ in protocol layering, error correction, and the software stack required to make chiplets from different vendors behave as a single logical device.

Semiconductor Engineering published a detailed comparison in late June that highlighted the fork in the road facing design teams. UCIe wraps a PCIe-compatible or streaming protocol in a standardised physical layer that supports both standard and advanced packaging, with the advanced option targeting bump pitches down to 25 microns and shoreline bandwidth density exceeding 1.3 terabytes per second per millimetre of die edge. BoW is physically simpler, designed for parallel interfaces without the full protocol stack, making it attractive for designs where the chiplet ecosystem is controlled by a single vendor and interoperability with third-party dies is not a requirement.

The choice between UCIe and BoW is not merely technical. It is a bet on how open the chiplet marketplace will actually become. UCIe's protocol compatibility with PCIe and CXL means that, in theory, an accelerator chiplet from one vendor could plug into a CPU socket designed by another and be addressable through a standard software driver stack. The reality, as the Semiconductor Engineering analysis noted, is that the physical layer for the most aggressive UCIe configurations demands such tight co-design of bump metallurgy, substrate routing, and power delivery that the practical interoperability of high-performance chiplets from different fabs remains aspirational rather than operational.

What the Substrate Tells You

Glass substrates are the other vector to watch. At the ECTC conference in June, Intel, TSMC, and several Korean substrate manufacturers presented data on through-glass vias, the vertical interconnects that replace through-silicon vias when the substrate itself is made of glass rather than silicon or organic laminate. TechTimes reported that the combined market for fan-out panel-level packaging and glass-core substrates is on track to grow more than tenfold over the next five years. SKC's Absolics subsidiary and Samsung Electro-Mechanics are both investing in glass substrate production capacity, targeting qualification with leading-edge logic customers by late 2027.

The appeal of glass is dimensional. Organic substrates warp under thermal cycling because the copper traces and the epoxy-based dielectric expand at different rates. That warpage limits how large a package substrate can be and how finely its traces can be patterned. Glass has a coefficient of thermal expansion closer to silicon, which means a large glass substrate stays flatter during assembly and operation, enabling larger interposers and tighter bump pitches. Intel's glass substrate programme, first disclosed publicly in 2023, aims to support package substrates of 100mm by 100mm or larger by the end of the decade.

What all of these developments point toward is a semiconductor industry in which packaging, not front-end process scaling, determines the pace of performance improvement for AI workloads. TSMC is still the dominant force, but the CoWoS bottleneck has created the first credible rationale for diversifying advanced packaging supply in a decade. Intel's EMIB and glass substrate programmes give it a differentiated asset to sell to foundry customers at a moment when its front-end node roadmap is still proving itself. Samsung's hybrid bonding data provides a measurable thermal advantage that HBM4 customers will need, whether they buy from Samsung, SK Hynix, or Micron. And the UCIe versus BoW debate will determine how many discrete chiplet suppliers actually emerge versus how many chiplet designs remain captive to a single vertically integrated vendor.

The number to watch is not a process node. It is the monthly CoWoS wafer capacity utilisation rate. If it dips below 90 percent without AI demand falling, that means CoPoS panel production or a competitor's alternative has begun to clear the queue. If it stays above 95 percent through 2027, the packaging bottleneck has not been relieved, and the scramble for interposer allocation will define the AI chip market as much as any architecture choice.