MediaTek Adopts Intel EMIB for AI ASICs, Eroding TSMC's Grip

MediaTek is now using Intel's EMIB packaging alongside TSMC's CoWoS for its AI ASIC designs, Crypto Briefing reported on 30 May, targeting a 26% share of the AI ASIC market by 2028. The decision marks the first time a major fabless customer has publicly split its advanced-packaging orders between the two foundries for a single product family. It is not a technology evaluation or a pilot. It is volume procurement, driven by the simple fact that TSMC's CoWoS lines cannot build interposers fast enough to meet demand from Nvidia, Broadcom, AMD, and the hyperscaler ASIC programs that have all converged on the same packaging technology at the same moment.

For two years the AI chip shortage narrative focused on H100 lead times and wafer allocation at TSMC's N4 and N3 nodes. That diagnosis was incomplete, and it is now provably wrong. The real bottleneck sits one step after the fab: in the advanced packaging facility where logic dies are bonded to high-bandwidth memory on a silicon interposer. 24/7 Wall St argued on 6 May that investors have systematically misdiagnosed where the AI chip shortage actually resides, and that the packaging layer is where Nvidia's dominance becomes a supply-chain problem for everyone else. When TSMC allocates CoWoS capacity, Nvidia gets first call. Everyone else queues.

The numbers are stark. TSMC is constructing or planning roughly 18 new fabrication and packaging plants simultaneously, Morning Overview reported on 21 May, in what the company describes internally as the largest concurrent buildout in its history. New CoWoS capacity coming online in the second half of 2026 will roughly double what was available at the end of 2025, but even that will not clear the backlog. Demand is rising faster than the tools can be installed. Applied Materials and ASML executives have both noted on recent earnings calls that lead times for packaging equipment have stretched past twelve months.

This is the structural opening into which Intel has inserted EMIB, its embedded multi-die interconnect bridge. The technology is not new. Intel shipped EMIB in products as far back as 2017 with the Stratix 10 FPGA, and it was a core element of the Ponte Vecchio datacenter GPU and the Sapphire Rapids Xeon. What is new is that Intel is now offering EMIB as a standalone foundry service, decoupled from Intel's own process nodes, to fabless customers who want to design chips that use TSMC's front-end but need a packaging path that is not gated by TSMC's CoWoS backlog.

The technology itself is a study in trade-offs. Where TSMC's CoWoS uses a full silicon interposer spanning the entire package, EMIB embeds small silicon bridge dies only where high-density interconnects are needed, directly into the organic substrate. Intel argued in a January 2026 presentation covered by Wccftech that this approach saves cost, simplifies design, and provides more flexibility than a monolithic interposer. The claim is not merely marketing. An interposer the size of a full reticle is expensive and yield-limited; a few small bridge dies in an otherwise standard organic substrate are cheaper and can scale more easily across different package dimensions.

What EMIB is not good at is maximum bandwidth density across an entire chip. A full interposer can route tens of thousands of signals between any two points on the package. EMIB provides high-density links only at the bridge locations, which means the floorplan must be designed around the bridges. For an Nvidia GPU with eight HBM stacks and a massive compute die, a full interposer remains the right answer. For an AI ASIC with a more modest die count, or a chiplet-based design that already partitions compute into discrete tiles, EMIB's bridging approach fits naturally. MediaTek's ASIC designs, which target cloud inference and edge-AI workloads rather than the absolute largest training clusters, sit squarely in that second category.

The MediaTek decision is not an isolated data point. Intel shares surged in mid-May on reports that SK hynix is in joint R&D discussions with Intel on 2.5D packaging using EMIB, adding the world's second-largest memory maker to the list of companies exploring alternatives to a TSMC-only packaging supply chain. Earlier in 2026, Google committed to building its next-generation TPUs at Intel Foundry, a deal that Barchart reported sent Intel's stock sharply higher on 10 June. The common thread across these announcements is not that Intel has caught TSMC on transistor density. It has not. The common thread is that Intel's packaging portfolio, accumulated over a decade of internal product development and now available to external customers, provides an alternative to a CoWoS monopoly that is fully subscribed.

Francis Sideco of TIRIAS Research laid out the argument explicitly in a 20 May Forbes column. "The focus has been on Intel Foundry's ability to compete on fab process nodes," Sideco wrote in Forbes. "But advanced packaging is the foundation on which it is building its success." The column noted that Intel Foundry's packaging customer engagements now span Apple, AWS, Cisco, Google, Microsoft, Nvidia, and Tesla, though the specific status of each engagement varies and not all have been publicly confirmed.

The focus has been on Intel Foundry's ability to compete on fab process nodes. But advanced packaging is the foundation on which it is building its success., Francis Sideco, TIRIAS Research, writing in Forbes, 20 May 2026

The chiplets conversation has shifted from whether to how many. At the Chiplet Summit in February 2026, Barry Pangrle reported for Semiconductor Engineering that the economic case for disaggregation now extends beyond the obvious candidates. Jim Handy of Objective Analysis and Jawad Nasrullah from Palo Alto Electron laid out predictions showing chiplet adoption accelerating not just for datacenter silicon but for networking ASICs and automotive processors. The driver is yield. A monolithic die at N3 or N2, approaching the reticle limit of roughly 800 square millimetres, carries defect risks that partition the same logic across two or four smaller dies can mitigate. Packaging becomes the discipline that makes the yield math work.

Hybrid bonding is the next rung on that ladder, and it is where the technology choices become genuinely divergent. TSMC's CoWoS roadmap adds hybrid bonding for vertical stacking. Intel's Foveros Direct, the evolution of its face-to-face die-stacking technology, pushes bump pitches below 10 microns. Both companies are targeting the same problem: HBM4 will require significantly higher interconnect density between logic and memory, and the industry-standard UCIe specification for chiplet-to-chiplet links demands physical-layer bandwidth that interposers alone will struggle to deliver. Intel's EMIB-T variant, detailed by Paul Alcorn at Tom's Hardware in May 2025, is designed explicitly for HBM4 integration and higher UCIe bandwidth, with improved power delivery and signal integrity compared to the current EMIB generation.

None of this means Intel is winning the foundry war on the front end. TSMC remains the dominant manufacturer of advanced logic by a wide margin, and its 2nm ramp in Kaohsiung, where five fabs are being built simultaneously, will extend that lead. Every wafer through 2026 is already sold, according to Morning Overview's reporting on 5 May. But the advanced-packaging bottleneck is a different kind of constraint than a process-technology gap. It is a capacity problem, not a capability problem, and capacity problems can be solved by adding a second supplier. That is what MediaTek just did.

The broader supply-chain implication is that advanced packaging is undergoing the same structural shift that logic manufacturing underwent in the 2010s, when the number of leading-edge fabs contracted to three. Today there are effectively two advanced-packaging providers at scale, TSMC and Intel, with Samsung's I-Cube and H-Cube efforts still building out and ASE and Amkor competing in the outsourced assembly-and-test layer beneath them. For fabless chip designers, dual-sourcing packaging is becoming as strategic as dual-sourcing wafer fabrication was a decade ago. The difference is that packaging choices are harder to abstract away. A chip designed for CoWoS cannot simply be dropped into an EMIB flow without re-engineering the floorplan and the physical-layer interface.

The cost differential matters. A full-reticle silicon interposer at TSMC's advanced CoWoS variants costs thousands of dollars per unit, and yield losses on large interposers increase non-linearly with area. Intel's EMIB, by replacing most of that silicon area with organic substrate and only embedding small bridge dies, claims a bill-of-materials advantage that becomes significant at volume. Wccftech's Hassan Mujtaba reported that Intel's internal analyses show EMIB saving between 30 and 50 percent on packaging cost compared to a full-interposer approach for certain die configurations. Those numbers are self-serving and should be treated accordingly, but the directional logic is sound: less silicon area means lower cost, all else being equal.

For Nvidia, the CoWoS bottleneck is an annoyance that constrains upside. For the ASIC designers competing with Nvidia in the inference market, it is an existential problem. A startup or a second-tier cloud provider trying to bring a custom inference chip to market cannot afford to wait eighteen months for CoWoS allocation behind Nvidia's Blackwell and Rubin orders. Intel's EMIB foundry service, by offering a packaging path with available capacity, changes the competitive dynamics at exactly the point where the market is fracturing. The hyperscalers are all designing their own inference chips. They need packaging. Intel has it.

What to Watch

The next checkpoint is Intel's Q3 2026 earnings call, where CEO Lip-Bu Tan is expected to provide an update on foundry customer count and the revenue trajectory of the packaging business line. Tan, who took the CEO role earlier this year, has already signaled that foundry gains are accelerating, touting balance sheet progress and AI CPU demand in late May. Separately, the industry will be watching for any announcement from Nvidia regarding foundry diversification. DigiTimes reported in January that Nvidia is planning to tap Intel's foundry for next-generation GPU production, though neither company has confirmed the arrangement. If Nvidia places even a partial packaging order with Intel, the CoWoS monopoly narrative ends.

The MediaTek decision, the SK hynix talks, the Google TPU deal, and the persistent CoWoS backlog together form a pattern that is larger than any single announcement. The silicon supply chain is being reconfigured not by a breakthrough process node but by the mundane reality that there is exactly one company in the world that can build a full-reticle silicon interposer in volume, and that company's lines are full. Intel has spent fifteen years developing EMIB and Foveros for its own products. The foundry strategy now asks whether those technologies can become an industry utility. MediaTek just voted yes.