TSMC CoWoS Capacity Sold Out Through 2027: The Packaging Wars Begin

Taiwan Semiconductor Manufacturing Co. plans to open an advanced chip packaging plant in Arizona by 2029, an executive told Reuters on April 22. The disclosure lands at a moment when TSMC's CoWoS capacity, the linchpin of the AI accelerator supply chain, is effectively sold out through 2027. Nvidia alone consumes an estimated 60 percent of CoWoS output, a figure DIGITIMES reported in late 2024, and the gap between demand and available interposer-based packaging has become the primary bottleneck throttling H100 and Blackwell deployments.

The Arizona facility will handle CoWoS and TSMC's SoIC 3D stacking, extending a packaging supply chain that today is concentrated almost entirely in Taiwan. The buildout is not charity. Global semiconductor sales hit $298.5 billion in Q1 2026, a 25 percent sequential jump, according to industry data reported in early May. Every dollar of that growth presses harder on the back-end: if you cannot package a die, you cannot ship a GPU, and if you cannot ship a GPU, the hyperscaler capex cycle seizes. The packaging constraint has become the most expensive finite resource in semiconductor manufacturing, and TSMC's rivals know it.

Intel is the most determined challenger. The company is in advanced talks with Google and Amazon to supply advanced packaging services for custom AI ASICs, with CFO Dave Zinsner signalling that deals could be worth billions of dollars annually, 24/7 Wall St reported in early April. Intel's pitch rests on EMIB-T, its Embedded Multi-die Interconnect Bridge, which it positions as a lower-cost alternative to CoWoS for AI inference chips that do not require the full reticle-scale interposer TSMC sells at a premium. DIGITIMES reported on May 7 that Intel is specifically targeting entry-level advanced packaging, a segment where TSMC's allocation has grown thinnest as its most advanced capacity is reserved for Nvidia and AMD.

The Wired feature by Lauren Goode, published April 6, details how Intel's New Mexico facilities, Fab 9 and Fab 11X, have been repurposed as dedicated advanced-packaging plants, funded in part by $500 million from the U.S. CHIPS Act. These are not leading-edge logic fabs. They are assembly-and-test sites re-engineered for die-to-die interconnect at pitches that were lab curiosities five years ago. Intel's bet is that packaging, not transistor density, will be the differentiator that decides which foundry wins the next wave of hyperscaler silicon.

Advanced chip packaging is suddenly at the center of the AI boom. Intel is going all in., Wired, April 6, 2026

The numbers bear out the urgency. TSMC is committing $56 billion in 2026 to expand AI chip output, including five new 2nm fabs and a 70 percent annual 2nm capacity ramp through 2028, according to industry reports from late April. But wafer starts without packaging capacity are an inventory problem, not a revenue line. Even as TSMC doubles CoWoS output, the queue lengthens. MSN reported on April 9 that Nvidia has locked in a dominant share of the world's most advanced packaging capacity, concentrating its supply chain around a small number of overseas partners even as U.S. government efforts to onshore packaging lag demand by at least three years.

What the Arizona plant will not do is close that gap before 2028 at the earliest. TSMC's packaging operations in Taiwan remain the sole source of CoWoS-L, the variant Nvidia uses for Blackwell-class products. CoWoS-L replaces the monolithic silicon interposer of CoWoS-S with a composite of smaller silicon bridges embedded in an organic substrate, a design that reduces interposer cost and improves yield at the expense of design complexity. Nvidia shifted the majority of its Blackwell production to CoWoS-L in early 2025, Yahoo Finance reported in January 2025, a move that freed CoWoS-S capacity for other customers while making Nvidia even more dependent on TSMC's single-source packaging line.

The supply concentration explains why Intel's EMIB-T pitch is landing. EMIB places small silicon bridge chips embedded in the package substrate to connect adjacent dies at high density, without the large interposer that makes CoWoS expensive. For an inference ASIC with two or four compute chiplets and a modest HBM stack, EMIB delivers enough bandwidth at roughly 40 percent lower packaging cost than an equivalent CoWoS-S design, an estimate DIGITIMES cited from industry sources. Google and Amazon both design inference silicon at volumes that make that delta worth eight figures a year. Intel's Q1 2026 earnings, reported by CNBC on April 23, showed revenue up more than 7 percent, with the stock surging 20 percent, driven in part by the packaging-services narrative that Wall Street had ignored for two years.

But the packaging conversation is not only about who builds the interposer. It is also about how dies connect to each other, and at what pitch. This is where hybrid bonding enters. Unlike microbump-based approaches that rely on solder joints at 30 to 50 micron pitch, hybrid bonding fuses copper pads directly across a dielectric bond interface, at pitches below 10 microns and trending toward 1 micron in research settings. The result is a connection density roughly 10,000 times higher than the best microbump arrays, with parasitic capacitance low enough to make die-to-die communication look like on-chip routing.

CEA-Leti, the French research institute that has driven much of the foundational work on direct-bond interconnects, will present its latest advances at ECTC 2026, Silicon Semiconductor reported on May 1. The work focuses on scaling hybrid bonding to submicron pitches and improving the cleanliness and planarity of the bonding surfaces, the two variables that determine whether a bond interface yields 99.99 percent of its connections or 85 percent. In production, anything below 99.9 percent across a die with 10,000 connections is scrap. Leti's research targets the defect mechanisms that appear when copper pads shrink below 500 nanometres, including dishing during CMP and void formation during anneal.

Semiconductor Engineering reported on March 2 that fab processes for hybrid bonding are now optimising for nanotwinned copper and SiCN dielectric deposition, which lower the anneal temperature required for copper grain growth and reduce the risk of thermal-mismatch stress across the bonded stack. Lower anneal temperatures matter because they allow hybrid bonding to be applied to HBM stacks, where DRAM layers cannot tolerate the 350 degrees Celsius that logic-to-logic bonding once required. Samsung and SK hynix are both pursuing hybrid-bonded HBM4 stacks for 2027, and the thermal budget is the gating factor.

What chiplets did not choose to be

The third leg of the packaging story is chiplet integration, and it is defined as much by what it deliberately leaves out as by what it includes. The Universal Chiplet Interconnect Express standard, UCIe, reached version 3.0 in early 2026, Electronic Design reported on March 10. UCIe 3.0 adds support for longer-reach die-to-die links across organic substrates, new power-management states for chiplet-level gating, and a compliance framework that makes it harder to call a proprietary interface UCIe-compatible without actually interoperating.

What UCIe 3.0 does not do is standardise the physical layer at the tightest pitches. The standard covers both advanced packaging, where pitch is below 25 microns and hybrid bonding is the presumed physical layer, and standard packaging, where pitch is above 100 microns and conventional flip-chip microbumps suffice. The advanced-packaging column of the standard deliberately underspecifies the physical implementation, because the industry has not converged on a single hybrid-bonding protocol. TSMC's SoIC uses one variant, Intel's Foveros Direct another, and Leti's research platform a third. UCIe provides the logical and protocol layers and leaves the bond interface to the foundry. That is not indecision. It is a recognition that the physical layer is where the foundries compete, and no standards body will make them converge.

The 2026 Chiplet Summit, held in February, surfaced a growing tension between the UCIe vision of a multi-vendor chiplet marketplace and the reality that most chiplet-based designs ship from a single foundry. Electronic Design noted that while UCIe 3.0 compliance is broadening, the number of tape-outs that mix dies from TSMC, Intel, and Samsung in a single package remains negligible. The bottleneck is not the protocol. It is the physical design kit mismatch, the thermal modelling gap when dies from different processes sit on the same interposer, and the absence of a commercial model for third-party chiplet IP that makes economic sense at volumes below 100,000 units.

Sarcina, a packaging IP startup, announced on April 9 that it is launching UCIe-A/S packaging IP designed to reduce the complexity of chiplet interconnect and accelerate time-to-market. The product targets the standard-packaging column of the UCIe spec, where pitch is relaxed and the barrier to entry is lower. Sarcina's bet is that the volume chiplet market will emerge first in the standard-packaging tier, where the cost of designing a custom interposer is not justified and off-the-shelf bridge chips have room to compete.

The bottleneck you cannot lithograph away

The packaging supply chain contains a structural mismatch that transistor scaling does not. A leading-edge 2nm wafer takes roughly three months to process. The same wafer, if it requires CoWoS-L packaging, spends another five to six months in back-end processing, including interposer fabrication, die stacking, underfill, and test. Packaging is now the longer pole in the tent. TSMC's $56 billion capex number sounds enormous until you realise that most of it goes to front-end capacity, not to the packaging lines where the real queue forms.

This is the gap Intel intends to fill. Its New Mexico fabs are not competing on transistor density, where TSMC holds a clear lead on 2nm and 3nm. They are competing on turnaround time for a service TSMC's biggest customers cannot get enough of. Intel's EMIB technology has been in production since 2017 in its own Stratix 10 FPGAs, which means it has a decade of yield-learning on embedded bridge interconnect that no other foundry can replicate quickly. The question is whether Intel's foundry organisation, which has historically served internal customers, can meet the yield and delivery requirements of Amazon and Google, whose internal ASIC teams operate on timelines that do not forgive a three-month slip.

Apple, meanwhile, has reportedly chosen Intel for advanced packaging on an upcoming chip, Investing.com reported on May 11. The report cited Amazon and Cisco as existing packaging customers and described Intel's customer pipeline as "turning into a customer avalanche." If confirmed, an Apple win would validate Intel's packaging-first foundry strategy more decisively than any number of CHIPS Act disbursements. Apple has spent a decade building a supply chain in which TSMC is the sole provider of advanced silicon. If it now carves out packaging as a separate sourcing decision, the industry will follow.

The Intel narrative received another jolt in early April when the company announced it would join the Terafab project alongside SpaceX, xAI, and Tesla, Forbes reported on April 10. Terafab is a $25 billion AI chip initiative that requires massive packaging throughput, and Intel's role as the packaging partner signals that even Elon Musk's notoriously aggressive internal chip team sees no faster path to volume than buying packaging services from someone who has already debugged the line.

What is coming into focus is a packaging landscape that will look very different in 2028 than it did in 2024. TSMC will have Arizona packaging capacity online but not at volume. Intel will have proven whether its EMIB foundry business can scale beyond a handful of anchor customers. Hybrid bonding will have moved from HBM research into HBM4 production, and the thermal-budget problem will have been solved or exposed as intractable. UCIe 3.0 will have either enabled the first genuine multi-foundry chiplet product or demonstrated that the chiplet marketplace remains a conference-slide concept. And the CoWoS queue, which today stretches past 18 months for new customers, will have either shortened or become the permanent cost of doing business in AI silicon. The next checkpoint is ECTC 2026 in late May, where CEA-Leti's hybrid-bonding results will be measured not by the pitch they achieve in the lab, but by the defect density they report at production-relevant throughput. Everything else is colour.