TSMC's 2nm Wafer Supply Through 2026 Is Already Sold Out

TSMC's 2-nanometer capacity through the end of 2026 is fully booked. Not mostly booked. Not booked with a few allocation slots held in reserve for strategic customers. Zero wafers remain unclaimed. Every chip the company can manufacture on its N2 node, across the five fabrication plants now coming online in Kaohsiung, Taiwan, has already been committed to customers building silicon for artificial intelligence and high-performance computing workloads, industry analysts reported in May.

That fact, stark on its own, becomes more remarkable when placed against the scale of the ramp. At its 2026 North America Technology Symposium, TSMC disclosed it is doubling the pace of advanced-node capacity expansion. Senior Vice President Hou Yongqing confirmed that five N2 fabs are set to enter production in 2026 alone, a concentration of leading-edge capacity at a single site that TechNode reported dwarfs anything the company has attempted for a single node. The compound annual growth rate for N2 capacity is projected at 70 percent through 2028. Even that will not clear the backlog.

The bottleneck is not demand; it is physics, tooling, and the sheer difficulty of scaling gate-all-around transistors at volume. N2 is TSMC's first node using GAA nanosheet architecture, a departure from the FinFET structure the industry has relied on since the 16nm generation. The transition requires new epitaxy steps, new etch chemistries, and new metrology. Every tool in the flow changes. TSMC is building out five fabs simultaneously because no single fab can hold enough EUV scanners to meet the wafer volume Apple, Nvidia, AMD, Broadcom, and Intel have collectively reserved. The capital expenditure required is reflected in TSMC's reported price hikes of 5 to 10 percent across all advanced nodes, Tom's Hardware reported in late June.

The capacity crunch at TSMC is reshaping customer behaviour in ways that ripple across the entire foundry landscape. Tom's Hardware reported in mid-2025 that Intel had placed orders with TSMC for N2 production capacity, with Nova Lake cited as the likely candidate. That an IDM with its own advanced-node ambitions would reserve N2 wafers from its largest manufacturing rival is an acknowledgment of two realities: TSMC's process lead is real, and Intel's own 18A ramp will not cover the full volume Intel needs for its client products in the 2026-2027 window.

Intel's 18A, meanwhile, has entered mass production with Panther Lake processors at the company's Oregon fab, and the performance-enhanced 18A-P variant reached risk production in June 2026, CNBC reported. The 18A-P node, detailed at the 2026 VLSI Symposium, delivers roughly 9 percent additional performance at the same power envelope, with backward compatibility for existing Panther Lake designs. Intel CEO Lip-Bu Tan told CNBC in May that the foundry business is gaining momentum, with improving manufacturing yields helping attract outside customer interest. That interest crystallised in a preliminary agreement between Apple and Intel, first reported by The Wall Street Journal and subsequently confirmed by President Trump in a June 2026 announcement that sent Intel's stock up 10.5 percent.

The Apple-Intel arrangement, while preliminary, is strategically legible. Apple has spent a decade diversifying away from single-source dependency and has a stated interest in US-based manufacturing for geopolitical resilience. Intel's 18A and 18A-P nodes, with their PowerVia backside power delivery and RibbonFET gate-all-around architecture, are competitive on paper with TSMC's N2 in density and power characteristics. The question is whether they are competitive in yield. Reuters noted in its analysis that actual production volumes under any Apple-Intel deal remain years away, and the agreement functions more as a strategic option than an imminent volume commitment. That timeline matters because it keeps Intel in the conversation without forcing an immediate yield competition it might not win.

Samsung Foundry enters this picture from a different, more constrained position. The company slashed its foundry investment by roughly half to $3.5 billion, Tom's Hardware reported in mid-2025, a cut that signals capital discipline but also cedes ground in the capacity race. Samsung's 2nm process, branded SF2, uses its own GAA implementation and was originally positioned to enter risk production ahead of TSMC's N2. The timeline has slipped. The company's Taylor, Texas fab, a cornerstone of its US manufacturing strategy, received its first chemical supply shipments from ENF Technology only in April 2026, TechTimes reported, a milestone that arrived roughly two years later than the original production schedule.

Yet Samsung is not without leverage. The same TSMC capacity crisis that drove Intel to book N2 wafers is driving customers toward Samsung as a second source. Samsung's foundry division posted record operating profit in Q1 2026, Gizmochina reported, as fabless customers facing N2 allocation constraints at TSMC turned to Samsung's mature 3nm and 4nm nodes for less performance-critical designs. Samsung vice chairman Jun Young-hyun met Nvidia CEO Jensen Huang in Seoul in June 2026 to discuss HBM4E memory supply and potential LP40 foundry engagements, TechTimes reported. Nvidia's interest in qualifying Samsung for advanced packaging and logic is not altruistic; it is a hedge against the concentration risk of having every H100, H200, B100, and B200 derivative flow through a single foundry's advanced packaging line.

At the trailing edge, Samsung has secured a different kind of win. Intel itself placed a substantial order for Samsung's 8nm process to manufacture the Z990 chipset for its Nova Lake platform, Tom's Hardware reported, citing Korea's Hankyung. An IDM ordering chipsets from a rival foundry is unusual but not unprecedented; it reflects the reality that Intel's internal fabs are optimised for leading-edge logic, not cost-sensitive I/O dies. For Samsung, any Intel order on any node is strategically valuable, because it validates Samsung as a merchant foundry partner for a company that historically has been the most vertically integrated silicon manufacturer on the planet.

The yield question sits underneath all of these dynamics, and it is the variable that will determine whose roadmap wins and whose breaks. TSMC's N2 yield ramp, according to the sparse public data available, is tracking ahead of where N3 was at the same point in its development cycle. The company's Arizona fab, running N4 and N4P processes, posted a $514 million profit in its first full year of mass production, TechTimes reported, and the Q1 2026 profit alone exceeded the full 2025 figure, suggesting yields on the Arizona line are maturing faster than earlier overseas fab ramps. That datapoint is not directly about N2, but it speaks to TSMC's institutional ability to bring new fabs to economic yields quickly.

Intel's 18A yields, by contrast, have been described as "usable" for production but not yet at the levels that would make a foundry customer comfortable placing a high-volume order without a pricing subsidy. Tom's Hardware reported in late 2025 that Intel acknowledged 18A yields were sufficient to begin Panther Lake volume production but still trailed internal targets. The 18A-P variant entering risk production in mid-2026 is a performance-optimised shrink of the base 18A node, and its yield trajectory will be the real test. Risk production on a performance-enhanced variant of a node that has not yet reached mature yields on its base version is an ambitious schedule, which is the kindest way to describe it.

Samsung's SF2 yield situation is the least transparent of the three. The company has not publicly disclosed defect density or parametric yield figures for its 2nm GAA process. Industry analysts tracking tool shipments to Samsung's Hwaseong campus note that EUV scanner installation volumes are lower than what would be expected for a full 2nm ramp in 2026. The Taylor, Texas fab, designed for 2nm-class processes, has received process chemicals but has not yet begun wafer starts, and the $3.5 billion investment figure for 2025 suggests Samsung is pacing its 2nm rollout rather than racing it. That may be the rational choice given TSMC's locked-in customer base and Intel's subsidised push, but it also means Samsung risks arriving third to a market that rewards being first.

The supply-demand arithmetic across the three foundries creates a curious equilibrium in mid-2026. TSMC has more demand than it can serve, and its response is to build more fabs faster than it ever has. Total planned new fab count stands at roughly 18 worldwide, MSN reported in late May, spanning advanced nodes in Taiwan and Arizona, specialty nodes in Japan, and a fab in Dresden. Intel has a credible process in 18A and a marquee customer conversation in Apple, but volume commitments are conditional on yields that have not yet been demonstrated at scale. Samsung has balance-sheet discipline, a legacy-node buffer, and the Nvidia HBM relationship, but it does not yet have a 2nm beachhead in the merchant market.

What each foundry chose not to be good at is as revealing as what they are pursuing. TSMC chose not to be a domestic supplier for any single geography, betting that its Taiwan-centric manufacturing base plus a handful of overseas fabs would satisfy political demands without fragmenting its R&D colocation advantage. Intel chose not to remain a captive IDM, betting its future on becoming a merchant foundry in direct competition with the company from which it is simultaneously buying N2 wafers. Samsung chose not to match TSMC's capex cycle, betting that the AI boom would create enough overflow demand to fill its fabs without requiring it to win the spending war.

Where the bottleneck actually sits

The bottleneck in the advanced-node foundry market in 2026 is not lithography tool availability, though ASML's high-NA EUV backlog extends years into the future. It is not materials, though GAA-specific precursors and specialty chemicals remain on tight allocation. The bottleneck is integration engineering. Bringing a GAA nanosheet process to economic yield requires tuning hundreds of interdependent parameters across epitaxy, atomic layer deposition, selective etch, and contact metallisation. Each fab ramp is a distinct learning curve, because tool configurations, cleanroom environments, and process recipes do not transfer identically between sites. TSMC's decision to build five N2 fabs simultaneously in Kaohsiung is a bet that it can parallelise those learning curves. The 70 percent CAGR target implies that by 2028, TSMC expects to be shipping roughly five times the N2 wafer volume it ships in 2026.

For Intel, the integration challenge is compounded by the fact that 18A is its first node to combine RibbonFET and PowerVia, and 18A-P is its first node to optimise that combination for performance. Each new process variant requires re-characterisation of the standard cell libraries, re-optimisation of the PDK for EDA tools, and re-qualification with customers. The Apple preliminary agreement, if it advances to a purchase order, will require Apple's silicon design teams to build test chips on an Intel PDK, validate against their internal signoff flows, and qualify packaging and test. That is a multi-year process even under aggressive timelines. Reuters framed it as "years away," and that framing is consistent with how semiconductor qualification cycles actually work.

Samsung's challenge is different. The Taylor fab delay means Samsung's US-based 2nm capacity will not be available until well after TSMC's Arizona N2 fab, which is scheduled to begin equipment installation in 2026. Samsung's GAA technology, branded MBCFET, is architecturally competitive, but the process integration team has cycled through multiple leadership changes, and the foundry business is operating at roughly half the investment level of its primary competitor. The 8nm order from Intel for the Nova Lake chipset is useful revenue, and the HBM4E discussions with Nvidia are strategically significant, but neither addresses the core question of whether Samsung can deliver 2nm yield at volumes large enough to compete for the next generation of AI accelerator orders.

The foundry market at the leading edge has never been concentrated in a single supplier to this degree. TSMC controls approximately 90 percent of the advanced-node foundry market below 7nm, and with N2, that share is trending higher, not lower, in the near term. The capacity crunch is not a temporary condition that will clear when new fabs come online; it is a structural feature of an industry where capital costs are rising faster than revenue per wafer, where only one company has demonstrated the ability to ramp GAA processes at volume, and where every hyperscaler and chip designer on the planet is chasing the same wafer starts.

The next milestone to watch is TSMC's Q2 2026 earnings call, where the company will provide its first revenue contribution from N2 wafers. That number, and the gross margin guidance attached to it, will reveal whether TSMC's price hikes are covering the depreciation cost of five simultaneous fab ramps or whether the N2 profitability curve looks different from previous node transitions. Intel's 18A-P yield update at the Intel Innovation event in September 2026 is the second checkpoint. Apple's silicon tape-out decisions for the A20 and M5 generations, expected to crystallise by late 2026, will determine whether the Intel-Apple preliminary agreement becomes real volume or remains a geopolitical placeholder. And Samsung's Q3 2026 earnings will show whether the record foundry profit in Q1 was a one-quarter phenomenon driven by TSMC overflow or the start of a sustainable second-source position.