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Anouk Devereaux
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Anouk Devereaux

Silicon Correspondent

Anouk Devereaux covers silicon for TechReaderDaily — the chips, the fabs, and the equipment that builds the equipment. Eindhoven base by design. She has been inside more cleanrooms than most people have been on factory tours.

19 articles published Eindhoven, Netherlands
  • transformer-only and inference-specialized ASICs
  • EUV lithography and the equipment supply chain
  • TSMC/Samsung/Intel Foundry process nodes and yield
  • packaging (CoWoS, hybrid bonding, chiplets)
  • the geopolitics of fab siting

Latest from this reporter

An artist's rendering of a chip package structure showing a processor and memory connected to a substrate through an array of interconnects. Hardware · Advanced Packaging

MediaTek Adopts Intel EMIB for AI ASICs, Eroding TSMC's Grip

As TSMC's CoWoS capacity struggles to meet AI silicon demand, MediaTek turns to Intel's embedded multi-die interconnect bridge technology for its AI ASIC production, signaling a split in advanced packaging orders that could reshape the foundry landscape.

Jun 17, 2026 · 9 min
A Google Tensor Processing Unit server rack assembly photographed during a facility tour, showing custom AI accelerator boards in a data center configuration. Hardware · Custom Silicon

Inference Chip Split as Google's TPU Fork Redraws ASIC Map

Google forking its TPU into separate training and inference dies at 2nm signals that the AI chip market is splitting, and for inference-only ASICs the crucial design question is no longer what a chip can do but what it can leave out.

Jun 2, 2026 · 8 min
How TSMC has mastered the geopolitics of chipmaking | The Economist Hardware · Geopolitics

TSMC's Geopolitical Fab Siting Redraws the Global Chip Map

TSMC's strategic fab placements across four jurisdictions reflect a shift where governments, not just markets, now dictate chip process node locations, and the 2028 production milestones will test whether this geopolitical experiment sustains the semiconductor supply chain.

May 14, 2026 · 7 min
Aerial view of TSMC's Phoenix, Arizona fabrication plant construction site with multiple large white buildings and cranes, April 2025. Hardware · Supply Chain

TSMC's 3nm Kumamoto Fab Proves Siting Is Now the Chip War

TSMC's upgrade of its second Japanese fab to 3-nanometer production is not a market move, but the latest proof that the geography of advanced silicon is now drawn by security planners, not supply-chain managers.

May 11, 2026 · 9 min
The Complete Enigma: EUV Lithography Machines and the Global ... Silicon · Supply Chain

EUV Supply Chain Bottleneck: Missing Lasers, Soaring Costs

ASML raised its 2026 revenue outlook to €40 billion, but the extreme ultraviolet lithography supply chain is maxed out, with optics, chemicals, and geopolitics straining under the load.

May 10, 2026 · 12 min
AMD and Nvidia GPUs Consume Lion's Share of TSMC's CoWoS Capacity | Tom ... Packaging · Supply Chain

TSMC's CoWoS at 98% Utilisation — Nvidia Secures Most

Advanced packaging has become the binding constraint on AI silicon, but hybrid bonding and chiplets offer a path out—though the supply chain is more concentrated than the front end ever was.

May 9, 2026 · 9 min
Intel Secures All Of ASML's High-NA EUV Lithography Machines Set To Be ... Hardware · Silicon Supply Chain

EUV Lithography's Real Bottleneck: 5,000 Suppliers Deep

While ASML's EXE:5200 High NA scanner ships and its light source targets 1,000 watts, the real bottleneck lies in a supply chain of 5,000 suppliers, where Zeiss mirrors and TRUMPF lasers each rely on a single factory on Earth.

May 9, 2026 · 9 min